1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a fuse area structure in a semiconductor device and a method of forming the same.
2. Description of the Related Art
Semiconductor devices are generally realized by stacking various material layer patterns and covering uppermost layers thereof with passivation films. Passivation films are generally formed of a hard material such as silicon nitride. The passivation film absorbs mechanical, electrical, and chemical shock, thus protecting the semiconductor device inside.
In general, semiconductor devices which include semiconductor memory devices can be subjected to a repair process, in which circuits that do not operate due to defects are replaced with redundant circuits. Alternatively, a trimming process can be performed to change the characteristics of some circuits to be suitable for a particular application. The repair process or the trimming process can be performed by cutting part of a predetermined interconnection by irradiating the interconnection with a laser. The interconnection cut by the laser is referred to as a fuseline. The cut part and an area which surrounds the cut part are referred to as a fuse area.
FIG. 1 is a sectional view showing part of the memory cell and the fuse area of a conventional semiconductor device, in particular, a DRAM device employing a multi-layer metal interconnection structure. On the left side of FIG. 1 is a cell array area, which includes a memory cell. The memory cell includes a transistor 14, 16, and 18; a capacitor 30, 32, and 34; multi-layer metal interconnections 38 and 42; interlayer dielectric films 20, 26, 36, and 40; and a passivation film 44. Also, on the right side of FIG. 1 is the fuse area, which includes a fuse line, that is, a bitline 24, connected to the drain region 16 of the transistor by a bitline contact plug 22. A fuse opening 50 is formed by etching the interlayer dielectric films 36 and 40 and the passivation film 44 on the fuse line 24 to a predetermined width. To activate the fuse, the laser beam is directed through the fuse opening 50, and the fuse line 24 under the fuse opening 50 is cut.
In this description, each of the interlayer dielectric films 20, 26, 36, and 40 is described as a single layer film. However, each can be a film obtained by stacking multi-layer insulating films. Also, a lower electrode contact plug 28 for electrically connecting the source region 18 of the transistor to a lower electrode 30 of the capacitor is located on a plane different from a plane on which the bitline 24 exists. Namely, the lower electrode contact plug 28 does not contact the bitline 24. Here, it is described that the bitline 24 is used as the fuse line. However, the wordline 14 may also be used as the fuse line. Also, another interconnection can be used as the fuse line in semiconductor devices other than memory devices.
The fuse area of the general semiconductor device having the structure as shown in FIG. 1 has certain drawbacks. The interlayer dielectric films 26, 36, and 40 exposed on the sidewall of the fuse opening 50 are formed of silicon oxide, in particular, boron phosphorous silicate glass (BPSG), phosphorous silicate glass (PSG), spin on glass (SOG), tetra ethyl ortho silicate (TEOS), and undoped silicate glass (USG), which have an excellent step coverage, in order to reduce a large step difference between a cell array area and a peripheral circuit area. However, the BPSG, the PSG, the SOG, and the TEOS which contain a large amount of impurities, for example, greater than or equal to 5 weight % of boron or greater than or equal to 4 weight % of phosphorous are vulnerable to moisture. The reliability of the semiconductor device in which the fuse area was formed is tested at a temperature of between 100 and 150xc2x0 C., a humidity of between 80 and 100%, and a pressure of between 1.5 and 3 atm. At this time, when moisture seeps into the interfaces between the interlayer dielectric films, which are vulnerable to the moisture, as shown in FIG. 2, interfaces between metal interconnections 38 and 42 formed of tungsten or aluminum and the interlayer dielectric films 36 and 40 under the metal interconnections 38 and 42 in an adjacent peripheral circuit are peeled from each other as denoted by reference numeral 52. Accordingly, the electrical resistance of a metal contact increases and the reliability of the semiconductor device is severely deteriorated. It seems, because the energy level of the interface between the layers is lower than the energy level inside the respective layers, that the moisture seeps into the interfaces between the interlayer dielectric films 26, 36, and 40 and the passivation film 44 and the interface between the interlayer dielectric films 36 and 40 and the metal interconnections 38 and 42.
In order to solve this problem, square guard rings 38xe2x80x2 and 42xe2x80x2 which surround the opening 50 as shown in FIG. 3 are provided in the invention disclosed in Japanese Patent Publication No. Hei 9-69571. The two-layered guard rings 38xe2x80x2 and 42xe2x80x2 and the multi-layered metal interconnections 38 and 42 are simultaneously formed of the same material, for example, aluminum. A ring-shaped etching stop film 34xe2x80x2 for stopping etching when the interlayer dielectric film 36 is etched in order to form a guard ring opening is formed under the guard ring 38xe2x80x2. The etching stop film 34xe2x80x2 and the capacitor upper electrode 34 are simultaneously formed of the same material, for example, polycrystalline silicon.
Therefore, using the guard rings 38xe2x80x2 and 42xe2x80x2, it is possible to prevent moisture from seeping into the interlayer dielectric films 36 and 40 of the sidewall of the fuse opening 50. Accordingly, it is possible to improve reliability of the semiconductor device. However, the semiconductor device is still vulnerable to the seeping of moisture into the interlayer dielectric film 26 around which the guard ring is not formed. In particular, the semiconductor device is still vulnerable to the seeping of moisture into interfaces between interlayer dielectric films 26, 36, and 40 and an interface between the guard rings 38xe2x80x2 and 42xe2x80x2, which are most vulnerable to moisture.
To solve the above problem, it is an object of the present invention to provide a fuse area structure in a semiconductor device, having a guard ring capable of preventing moisture from seeping into the sidewall of a fuse opening.
It is another object of the present invention to provide a method of forming a guard ring capable of preventing moisture from seeping into the sidewall of the fuse opening.
Accordingly, to achieve the first object, there is provided a fuse area structure in a semiconductor device having a multi-layer metal interconnection structure. The structure includes a ring-shaped guard ring which surrounds the fuse opening. The guard ring is integrally formed with the passivation film. The fuse area in the semiconductor device according to an aspect of the present invention includes a fuse line and multi-layered interlayer dielectric films formed on the fuse line, the multi-layered interlayer dielectric films forming insulating films between metals of the multi-layer metal interconnection. A passivation film covers the uppermost layer of the semiconductor device. A guard ring is integrally formed with the passivation film in the interlayer dielectric films on the fuse line excluding the interlayer dielectric film immediately adjacent to the fuse line. The guard ring fills a ring-shaped guard ring opening which surrounds an area in which the fuse line is to be cut. The fuse opening exposes the interlayer dielectric film that is immediately adjacent to the fuse line. The fuse opening is surrounded by the guard and is formed in the passivation film and the interlayer dielectric films under the passivation film.
According to an embodiment, the fuse area structure can further comprise a protection film formed by extending the passivation film on the sidewall of the fuse opening. The passivation film can be formed of a moisture-proof film such as a silicon nitride film, a silicon oxide film or a compound film of silicon nitride and silicon oxide.
In accordance with another aspect, the invention is directed to a method of forming a fuse area. In accordance with the method, a fuse line is formed, and a first interlayer dielectric film is formed on the fuse line. A ring-shaped guard ring opening etching stop film which surrounds an area in which a fuse opening is to be formed is formed on the first interlayer dielectric film using a predetermined conductive layer of a semiconductor device to be formed. A second interlayer dielectric film is formed on the guard ring opening etching stop film. A contact hole in which the contact of a peripheral circuit is to be formed is formed by etching a part of the second interlayer dielectric film. At the same time, a guard ring opening for exposing the guard ring opening etching stop film is formed in the fuse area. An upper interconnection layer is formed by depositing a conductive material which will form the upper interconnection layer of the semiconductor device on the entire surfaces of the contact hole and the guard ring opening and patterning the conductive material. At the same time, the conductive material deposited on the guard ring opening is removed. A guard ring is formed of the same material as a passivation film by exposing the first interlayer dielectric film by removing the exposed etching stop film of the guard ring opening and depositing the passivation film on the entire surfaces of the upper interconnection layer and the guard ring opening.
According to one embodiment of the present invention, the fuse opening can be formed in an area surrounded by the guard ring opening when the guard ring opening is formed. At this time, the etching stop film can be formed under the fuse opening.
Also, removal of the conductive material deposited on the guard ring opening or the fuse opening, and removal of the guard ring opening etching stopping film or the fuse opening etching stop film under the guard ring opening and the fuse opening, respectively, can be successively performed using etching gas or etching solution having low selectivity with respect to the conductive material and the etching stop films.
Also, it is preferable that the interface between the first interlayer dielectric film and the etching stop film be exposed on the sidewall of the guard ring opening or the fuse opening by slightly over etching the guard ring opening etching stop film or the fuse opening etching stop film when the guard ring etching stop film or the fuse opening etching stop film is removed.